#ifndef __QE_MMC_H__
#define __QE_MMC_H__



#include "qe_def.h"



/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
#define SD_VERSION_SD	(1U << 31)
#define MMC_VERSION_MMC	(1U << 30)

#define MAKE_SDMMC_VERSION(a, b, c)	\
	((((qe_u32)(a)) << 16) | ((qe_u32)(b) << 8) | (qe_u32)(c))
#define MAKE_SD_VERSION(a, b, c)	\
	(SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
#define MAKE_MMC_VERSION(a, b, c)	\
	(MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))

#define EXTRACT_SDMMC_MAJOR_VERSION(x)	\
	(((qe_u32)(x) >> 16) & 0xff)
#define EXTRACT_SDMMC_MINOR_VERSION(x)	\
	(((qe_u32)(x) >> 8) & 0xff)
#define EXTRACT_SDMMC_CHANGE_VERSION(x)	\
	((qe_u32)(x) & 0xff)

#define SD_VERSION_3		            MAKE_SD_VERSION(3, 0, 0)
#define SD_VERSION_2		            MAKE_SD_VERSION(2, 0, 0)
#define SD_VERSION_1_0		            MAKE_SD_VERSION(1, 0, 0)
#define SD_VERSION_1_10		            MAKE_SD_VERSION(1, 10, 0)

#define MMC_VERSION_UNKNOWN	            MAKE_MMC_VERSION(0, 0, 0)
#define MMC_VERSION_1_2		            MAKE_MMC_VERSION(1, 2, 0)
#define MMC_VERSION_1_4		            MAKE_MMC_VERSION(1, 4, 0)
#define MMC_VERSION_2_2		            MAKE_MMC_VERSION(2, 2, 0)
#define MMC_VERSION_3		            MAKE_MMC_VERSION(3, 0, 0)
#define MMC_VERSION_4		            MAKE_MMC_VERSION(4, 0, 0)
#define MMC_VERSION_4_1		            MAKE_MMC_VERSION(4, 1, 0)
#define MMC_VERSION_4_2		            MAKE_MMC_VERSION(4, 2, 0)
#define MMC_VERSION_4_3		            MAKE_MMC_VERSION(4, 3, 0)
#define MMC_VERSION_4_4		            MAKE_MMC_VERSION(4, 4, 0)
#define MMC_VERSION_4_41	            MAKE_MMC_VERSION(4, 4, 1)
#define MMC_VERSION_4_5		            MAKE_MMC_VERSION(4, 5, 0)
#define MMC_VERSION_5_0		            MAKE_MMC_VERSION(5, 0, 0)
#define MMC_VERSION_5_1		            MAKE_MMC_VERSION(5, 1, 0)

#define MMC_IS_SD(x)	                ((x)->version & SD_VERSION_SD)
#define MMC_IS_MMC(x)	                ((x)->version & MMC_VERSION_MMC)

#define QE_MMC_MAX_BLOCK_LEN            (512)

#define MMC_CAP(mode)		            (1 << mode)
#define MMC_MODE_HS		                (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
#define MMC_MODE_HS_52MHz	            MMC_CAP(MMC_HS_52)
#define MMC_MODE_DDR_52MHz	            MMC_CAP(MMC_DDR_52)
#define MMC_MODE_HS200		            MMC_CAP(MMC_HS_200)
#define MMC_MODE_HS400		            MMC_CAP(MMC_HS_400)
#define MMC_MODE_HS400_ES	            MMC_CAP(MMC_HS_400_ES)

#define MMC_MODE_8BIT		            QE_BIT(30)
#define MMC_MODE_4BIT		            QE_BIT(29)
#define MMC_MODE_1BIT		            QE_BIT(28)
#define MMC_MODE_SPI		            QE_BIT(27)

#define SD_DATA_4BIT	                0x00040000

#define MMC_STATE_PRG		            (7 << 9)

#define MMC_VDD_165_195		            0x00000080	/* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21		            0x00000100	/* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22		            0x00000200	/* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23		            0x00000400	/* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24		            0x00000800	/* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25		            0x00001000	/* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26		            0x00002000	/* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27		            0x00004000	/* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28		            0x00008000	/* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29		            0x00010000	/* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30		            0x00020000	/* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31		            0x00040000	/* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32		            0x00080000	/* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33		            0x00100000	/* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34		            0x00200000	/* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35		            0x00400000	/* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36		            0x00800000	/* VDD voltage 3.5 ~ 3.6 */

#define MMC_SWITCH_MODE_CMD_SET		    0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS	    0x01 /* Set bits in EXT_CSD byte addressed by index which are 1 in value field */
#define MMC_SWITCH_MODE_CLEAR_BITS	    0x02 /* Clear bits in EXT_CSD byte addressed by index, which are 1 in value field */
#define MMC_SWITCH_MODE_WRITE_BYTE	    0x03 /* Set target byte to value */

#define SD_SWITCH_CHECK		            0
#define SD_SWITCH_SWITCH	            1

/*
 * EXT_CSD fields
 */
#define MMC_EXT_CSD_ENH_START_ADDR		    136	/* R/W */
#define MMC_EXT_CSD_ENH_SIZE_MULT		    140	/* R/W */
#define MMC_EXT_CSD_GP_SIZE_MULT		    143	/* R/W */
#define MMC_EXT_CSD_PARTITION_SETTING	    155	/* R/W */
#define MMC_EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
#define MMC_EXT_CSD_MAX_ENH_SIZE_MULT	    157	/* R */
#define MMC_EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
#define MMC_EXT_CSD_RST_N_FUNCTION		    162	/* R/W */
#define MMC_EXT_CSD_BKOPS_EN		        163	/* R/W & R/W/E */
#define MMC_EXT_CSD_WR_REL_PARAM		    166	/* R */
#define MMC_EXT_CSD_WR_REL_SET		        167	/* R/W */
#define MMC_EXT_CSD_RPMB_MULT		        168	/* RO */
#define MMC_EXT_CSD_ERASE_GROUP_DEF		    175	/* R/W */
#define MMC_EXT_CSD_BOOT_BUS_WIDTH		    177
#define MMC_EXT_CSD_PART_CONF		        179	/* R/W */
#define MMC_EXT_CSD_BUS_WIDTH		        183	/* R/W */
#define MMC_EXT_CSD_STROBE_SUPPORT		    184	/* R/W */
#define MMC_EXT_CSD_HS_TIMING		        185	/* R/W */
#define MMC_EXT_CSD_REV			            192	/* RO */
#define MMC_EXT_CSD_CARD_TYPE		        196	/* RO */
#define MMC_EXT_CSD_PART_SWITCH_TIME	    199	/* RO */
#define MMC_EXT_CSD_SEC_CNT			        212	/* RO, 4 bytes */
#define MMC_EXT_CSD_HC_WP_GRP_SIZE		    221	/* RO */
#define MMC_EXT_CSD_HC_ERASE_GRP_SIZE	    224	/* RO */
#define MMC_EXT_CSD_BOOT_MULT		        226	/* RO */
#define MMC_EXT_CSD_GENERIC_CMD6_TIME       248 /* RO */
#define MMC_EXT_CSD_BKOPS_SUPPORT		    502	/* RO */

/*
 * EXT_CSD field definitions
 */

#define MMC_EXT_CSD_CMD_SET_NORMAL		    (1 << 0)
#define MMC_EXT_CSD_CMD_SET_SECURE		    (1 << 1)
#define MMC_EXT_CSD_CMD_SET_CPSECURE	    (1 << 2)

#define MMC_EXT_CSD_CARD_TYPE_26	        (1 << 0)	/* Card can run at 26MHz */
#define MMC_EXT_CSD_CARD_TYPE_52	        (1 << 1)	/* Card can run at 52MHz */
#define MMC_EXT_CSD_CARD_TYPE_DDR_1_8V	    (1 << 2)
#define MMC_EXT_CSD_CARD_TYPE_DDR_1_2V	    (1 << 3)
#define MMC_EXT_CSD_CARD_TYPE_DDR_52	    (MMC_EXT_CSD_CARD_TYPE_DDR_1_8V | \
                                             MMC_EXT_CSD_CARD_TYPE_DDR_1_2V)

#define MMC_EXT_CSD_CARD_TYPE_HS200_1_8V	QE_BIT(4)	/* Card can run at 200MHz */
						/* SDR mode @1.8V I/O */
#define MMC_EXT_CSD_CARD_TYPE_HS200_1_2V	QE_BIT(5)	/* Card can run at 200MHz */
						/* SDR mode @1.2V I/O */
#define MMC_EXT_CSD_CARD_TYPE_HS200		    (MMC_EXT_CSD_CARD_TYPE_HS200_1_8V | \
					                         MMC_EXT_CSD_CARD_TYPE_HS200_1_2V)
#define MMC_EXT_CSD_CARD_TYPE_HS400_1_8V	QE_BIT(6)
#define MMC_EXT_CSD_CARD_TYPE_HS400_1_2V	QE_BIT(7)
#define MMC_EXT_CSD_CARD_TYPE_HS400		    (MMC_EXT_CSD_CARD_TYPE_HS400_1_8V | \
					                         MMC_EXT_CSD_CARD_TYPE_HS400_1_2V)

#define MMC_EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
#define MMC_EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
#define MMC_EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
#define MMC_EXT_CSD_DDR_BUS_WIDTH_4	5	/* Card is in 4 bit DDR mode */
#define MMC_EXT_CSD_DDR_BUS_WIDTH_8	6	/* Card is in 8 bit DDR mode */
#define MMC_EXT_CSD_DDR_FLAG	            QE_BIT(2)	/* Flag for DDR mode */
#define MMC_EXT_CSD_BUS_WIDTH_STROBE        QE_BIT(7)	/* Enhanced strobe mode */

#define MMC_EXT_CSD_TIMING_LEGACY	        0	/* no high speed */
#define MMC_EXT_CSD_TIMING_HS	            1	/* HS */
#define MMC_EXT_CSD_TIMING_HS200	        2	/* HS200 */
#define MMC_EXT_CSD_TIMING_HS400	        3	/* HS400 */
#define MMC_EXT_CSD_DRV_STR_SHIFT	        4	/* Driver Strength shift */

#define MMC_EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
#define MMC_EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
#define MMC_EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
#define MMC_EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)

#define MMC_EXT_CSD_BOOT_ACK(x)		(x << 6)
#define MMC_EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
#define MMC_EXT_CSD_PARTITION_ACCESS(x)	(x << 0)

#define MMC_EXT_CSD_EXTRACT_BOOT_ACK(x)		(((x) >> 6) & 0x1)
#define MMC_EXT_CSD_EXTRACT_BOOT_PART(x)		(((x) >> 3) & 0x7)
#define MMC_EXT_CSD_EXTRACT_PARTITION_ACCESS(x)	((x) & 0x7)

#define MMC_EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
#define MMC_EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
#define MMC_EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)

#define MMC_EXT_CSD_PARTITION_SETTING_COMPLETED	(1 << 0)

#define MMC_EXT_CSD_ENH_USR		(1 << 0)	/* user data area is enhanced */
#define MMC_EXT_CSD_ENH_GP(x)	(1 << ((x)+1))	/* GP part (x+1) is enhanced */

#define MMC_EXT_CSD_HS_CTRL_REL	(1 << 0)	/* host controlled WR_REL_SET */

#define MMC_EXT_CSD_WR_DATA_REL_USR		(1 << 0)	/* user data area WR_REL */
#define MMC_EXT_CSD_WR_DATA_REL_GP(x)	(1 << ((x)+1))	/* GP part (x+1) WR_REL */


#define MMC_DATA_READ		            1
#define MMC_DATA_WRITE		            2

#define MMC_CMD_GO_IDLE_STATE		    0
#define MMC_CMD_SEND_OP_COND		    1
#define MMC_CMD_ALL_SEND_CID		    2
#define MMC_CMD_SET_RELATIVE_ADDR	    3
#define MMC_CMD_SET_DSR			        4
#define MMC_CMD5                        5
#define MMC_CMD_SWITCH			        6
#define MMC_CMD_SELECT_CARD		        7
#define MMC_CMD_SEND_EXT_CSD		    8
#define MMC_CMD_SEND_CSD		        9
#define MMC_CMD_SEND_CID		        10
#define MMC_CMD11                       11
#define MMC_CMD_STOP_TRANSMISSION	    12
#define MMC_CMD_SEND_STATUS		        13
#define MMC_CMD_SET_BLOCKLEN		    16
#define MMC_CMD_READ_SINGLE_BLOCK	    17
#define MMC_CMD_READ_MULTIPLE_BLOCK	    18
#define MMC_CMD_SEND_TUNING_BLOCK		19
#define MMC_CMD_SEND_TUNING_BLOCK_HS200	21
#define MMC_CMD_SET_BLOCK_COUNT         23
#define MMC_CMD_WRITE_SINGLE_BLOCK	    24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
#define MMC_CMD_ERASE_GROUP_START	    35
#define MMC_CMD_ERASE_GROUP_END		    36
#define MMC_CMD_ERASE			        38
#define MMC_CMD52                       52
#define MMC_CMD_APP_CMD			        55
#define MMC_CMD_SPI_READ_OCR		    58
#define MMC_CMD_SPI_CRC_ON_OFF		    59
#define MMC_CMD_RES_MAN			        62

#define MMC_CMD_APP_PREFIX              0x8000U
#define MMC_ACMD6	                    (MMC_CMD_APP_PREFIX + 0x0600U)
#define MMC_ACMD13                      (MMC_CMD_APP_PREFIX + 0x0D00U)
#define MMC_ACMD23	                    (MMC_CMD_APP_PREFIX + 0x1700U)
#define MMC_ACMD41	                    (MMC_CMD_APP_PREFIX + 0x2900U)
#define MMC_ACMD42	                    (MMC_CMD_APP_PREFIX + 0x2A00U)
#define MMC_ACMD51	                    (MMC_CMD_APP_PREFIX + 0x3300U)

#define MMC_CMD62_ARG1			        0xefac62ec
#define MMC_CMD62_ARG2			        0xcbaea7

#define SD_CMD_SEND_RELATIVE_ADDR	    3
#define SD_CMD_SWITCH_FUNC		        6
#define SD_CMD_SEND_IF_COND		        8
#define SD_CMD_SWITCH_UHS18V		    11

#define SD_CMD_APP_SET_BUS_WIDTH	    6
#define SD_CMD_APP_SD_STATUS	    	13
#define SD_CMD_ERASE_WR_BLK_START	    32
#define SD_CMD_ERASE_WR_BLK_END		    33
#define SD_CMD_APP_SEND_OP_COND	    	41
#define SD_CMD_APP_SEND_SCR	    	    51

static inline qe_bool mmc_is_tuning_cmd(qe_uint cmdidx)
{
	if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
	    (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
		return qe_true;
	return qe_false;
}

/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY	            0x00020000
#define SD_HIGHSPEED_SUPPORTED	        0x00020000

#define MMC_UHS_SDR12_BUS_SPEED	        0
#define MMC_HIGH_SPEED_BUS_SPEED	    1
#define MMC_UHS_SDR25_BUS_SPEED	        1
#define MMC_UHS_SDR50_BUS_SPEED	        2
#define MMC_UHS_SDR104_BUS_SPEED	    3
#define MMC_UHS_DDR50_BUS_SPEED	        4

#define SD_MODE_UHS_SDR12	            QE_BIT(MMC_UHS_SDR12_BUS_SPEED)
#define SD_MODE_UHS_SDR25	            QE_BIT(MMC_UHS_SDR25_BUS_SPEED)
#define SD_MODE_UHS_SDR50	            QE_BIT(MMC_UHS_SDR50_BUS_SPEED)
#define SD_MODE_UHS_SDR104	            QE_BIT(MMC_UHS_SDR104_BUS_SPEED)
#define SD_MODE_UHS_DDR50	            QE_BIT(MMC_UHS_DDR50_BUS_SPEED)

#define MMC_OCR_BUSY		            0x80000000
#define MMC_OCR_HCS			            0x40000000
#define MMC_OCR_S18R		            0x1000000
#define MMC_OCR_VOLTAGE_MASK	        0x007FFF80
#define MMC_OCR_ACCESS_MODE		        0x60000000

#define MMC_ERASE_ARG		            0x00000000
#define MMC_SECURE_ERASE_ARG	        0x80000000
#define MMC_TRIM_ARG		            0x00000001
#define MMC_DISCARD_ARG		            0x00000003
#define MMC_SECURE_TRIM1_ARG	        0x80000001
#define MMC_SECURE_TRIM2_ARG	        0x80008000

#define MMC_STATUS_MASK		            (~0x0206BF7F)
#define MMC_STATUS_SWITCH_ERROR	        (1 << 7)
#define MMC_STATUS_RDY_FOR_DATA         (1 << 8)
#define MMC_STATUS_CURR_STATE	        (0xf << 9)
#define MMC_STATUS_ERROR	            (1 << 19)

#define MMC_RSP_PRESENT                 (1 << 0)
#define MMC_RSP_136	                    (1 << 1)		/* 136 bit response */
#define MMC_RSP_CRC	                    (1 << 2)		/* expect valid crc */
#define MMC_RSP_BUSY	                (1 << 3)		/* card may send busy */
#define MMC_RSP_OPCODE	                (1 << 4)		/* response contains opcode */

#define MMC_RSP_NONE	                (0)
#define MMC_RSP_R1	                    (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b	                    (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
#define MMC_RSP_R2	                    (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3	                    (MMC_RSP_PRESENT)
#define MMC_RSP_R4	                    (MMC_RSP_PRESENT)
#define MMC_RSP_R5	                    (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6	                    (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7	                    (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)

#define MMC_PART_NOAVAILABLE	        (0xff)
#define MMC_PART_ACCESS_MASK	        (0x7)
#define MMC_PART_SUPPORT		        (0x1)
#define MMC_ENHNCD_SUPPORT		        (0x2)
#define MMC_PART_ENH_ATTRIB		        (0x1f)

#define MMC_QUIRK_RETRY_SEND_CID	    QE_BIT(0)
#define MMC_QUIRK_RETRY_SET_BLOCKLEN	QE_BIT(1)

/* Minimum partition switch timeout in units of 10-milliseconds */
#define MMC_MIN_PART_SWITCH_TIME	    30 /* 300 ms */

#define MMC_CMD8_VOL_PATTERN            0x1AA

enum mmc_bus_mode {
	MMC_LEGACY,
	SD_LEGACY,
	MMC_HS,
	SD_HS,
	MMC_HS_52,
	MMC_DDR_52,
	UHS_SDR12,
	UHS_SDR25,
	UHS_SDR50,
	UHS_DDR50,
	UHS_SDR104,
	MMC_HS_200,
	MMC_HS_400,
	MMC_HS_400_ES,
	MMC_MODES_END
};

#define MMC_UHS_CAPS                    (MMC_CAP(UHS_SDR12) | \
                                         MMC_CAP(UHS_SDR25) | \
		                                 MMC_CAP(UHS_SDR50) | \
                                         MMC_CAP(UHS_SDR104) | \
		                                 MMC_CAP(UHS_DDR50))

static inline qe_bool mmc_supports_uhs(qe_uint caps)
{
	return (caps & MMC_UHS_CAPS) ? qe_true : qe_false;
}

#define MMC_CLK_ENABLE		qe_false
#define MMC_CLK_DISABLE		qe_true

enum mmc_voltage {
	MMC_SIGNAL_VOLTAGE_000 = 0,
	MMC_SIGNAL_VOLTAGE_120 = 1,
	MMC_SIGNAL_VOLTAGE_180 = 2,
	MMC_SIGNAL_VOLTAGE_330 = 4,
};

#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
				                MMC_SIGNAL_VOLTAGE_180 |\
				                MMC_SIGNAL_VOLTAGE_330)

#define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)

/* Maximum block size for MMC */
#define MMC_MAX_BLOCK_LEN	    512

enum {
    MMC_CARD_SD = 1,
    MMC_CARD_MMC,
    MMC_CARD_SDIO,
    MMC_CARD_SDCOMBO,
    MMC_CARD_EMMC,
};

typedef struct 
{
    qe_uint host_caps;
    qe_uint voltages;
    qe_uint f_min;
    qe_uint f_max;
    qe_uint b_max;
    qe_u8 part_type;
} qe_mmc_config;

typedef struct 
{
    qe_u16 cmdidx;
    qe_uint resp_type;
    qe_uint cmdarg;
    qe_uint response[4];
} qe_mmc_cmd;

typedef struct 
{
    union {
        void *dest;
        const void *src;
    };
    qe_uint flags;
    qe_uint blocks;
    qe_uint blocksize;
} qe_mmc_data;

typedef struct {
	qe_uint au;		/* In sectors */
	qe_uint erase_timeout;	/* In milliseconds */
	qe_uint erase_offset;	/* In milliseconds */
} qe_sd_ssr;

struct qe_mmc_device;
typedef struct qe_mmc_device qe_mmc;

typedef struct 
{
    qe_ret  (*send_cmd)(qe_mmc *mmc, qe_mmc_cmd *cmd, qe_mmc_data *data);
    qe_ret  (*set_ios)(qe_mmc *mmc);
    qe_bool (*getcd)(qe_mmc *mmc);
    qe_bool (*getwp)(qe_mmc *mmc);
    qe_ret  (*execute_tuning)(qe_mmc *mmc, qe_uint opcode);
    qe_ret  (*host_power_cycle)(qe_mmc *mmc);
} qe_mmc_ops;

typedef struct qe_mmc_device
{
    qe_dev dev;
    qe_mmc_config *cfg;
    const qe_mmc_ops *ops;
    void *priv;
    qe_list list;

    qe_bool clk_disable;

    qe_u8 gen_cmd6_time;	/* units: 10 ms */
    qe_u8 part_switch_time;	/* units: 10 ms */
    qe_u8 part_config;
    qe_u8 part_support;
    qe_u8 part_attr;
    qe_u8 wr_rel_set;
    qe_u16 rca;
    qe_u32 quirks;
    qe_u32 high_capacity;
    qe_u32 signal_voltage;
    qe_u32 cardtype;		/* cardtype read from the MMC */
    qe_int ddr_mode;
    qe_uint ocr;
    qe_uint dsr;
    qe_uint scr[2];
	qe_uint csd[4];
	qe_uint cid[4];
    qe_uint dsr_imp;
    qe_uint clock;
    qe_uint version;
    qe_uint bus_width;
	qe_uint card_caps;
	qe_uint host_caps;
    qe_uint tran_speed;
    qe_uint legacy_speed;
    qe_uint read_bl_len;
    qe_uint write_bl_len;
    qe_uint erase_grp_size;	/* in 512-byte sectors */
    qe_uint lba;
    qe_uint hc_wp_grp_size;	/* in 512-byte sectors */

    qe_sd_ssr ssr;

    qe_u64 capacity;
	qe_u64 capacity_user;
	qe_u64 capacity_boot;
	qe_u64 capacity_rpmb;
	qe_u64 capacity_gp[4];

    qe_u64 enh_user_start;
    qe_u64 enh_user_size;

    enum mmc_voltage current_voltage;
    enum mmc_bus_mode selected_mode;
    enum mmc_bus_mode best_mode;

    qe_u8 *ext_csd;

    qe_uint has_init:1;
    qe_uint init_in_progress:1;
    qe_uint op_cond_pending:1;

} qe_mmc;



void 
qe_mmc_list_devices(void);

qe_ret 
qe_mmc_init_device(qe_mmc *mmc, qe_bool force_init);

qe_ret 
qe_mmc_register(qe_mmc *mmc, qe_const_str name, const qe_mmc_ops *ops, void *ptr);

qe_size
qe_mmc_bread(qe_mmc *mmc, qe_size start, qe_size blkcnt, qe_ptr dst);

qe_size
qe_mmc_bwrite(qe_mmc *mmc, qe_size start, qe_size blkcnt, qe_const_ptr src);

qe_size
qe_mmc_berase(qe_mmc *mmc, qe_size start, qe_size blkcnt);



#endif /* __QE_MMC_H__ */
